Wantong Li

Dr. Wantong Li

Biosketch

Wantong Li is an assistant professor of electrical and computer engineering at the University of California, Riverside, where he directs the Intelligent Computing Architecture and Nanosystem (ICAN) Group. He received the B.S. degree in electrical engineering from Washington University in St. Louis in 2015, and the M.S. degree in electrical engineering from Columbia University in 2016. He obtained the Ph.D. degree from Georgia Institute of Technology, where he was advised by Prof. Shimeng Yu. From 2017 to 2019, he worked as an IC design engineer at Power Integrations and Micron Technology. He also held internship positions at AMD, MediaTek, Roche Diagnostics, and bioMérieux.

Education

  • Ph.D., electrical and computer engineering, Georgia Institute of Technology, 2024
  • M.S., electrical engineering, Columbia University, 2016
  • B.S., electrical engineering, Washington University in St. Louis, 2015

Honors and Awards

  • ECE Interdisciplinary Research (INSPIRE) Fellowship, Georgia Tech
  • School of ECE Fellowship, Georgia Tech
  • Nikola Tesla Scholarship, Columbia University
  • Sigma Xi (Scientific Research Society)
  • Eta Kappa Nu (Electrical and Computer Engineering Honor Society)
  • Tau Beta Pi (Engineering Honor Society)

Service

Paper Reviews:
  • IEEE, Computer Architecture Letters (CAL)
  • IEEE, Journal of Solid-State Circuits (JSSC)
  • IEEE, Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)
  • IEEE, Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
  • IEEE, Transactions on Circuits and Systems for Artificial Intelligence (TCASAI)
  • IEEE, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
  • MDPI, Electronics
  • MDPI, Sensors

  • Springer, The Journal of Supercomputing

  • IEEE, International Conference on Artificial Intelligence Circuits and Systems (AICAS)
  • IEEE, International Symposium on Circuits and Systems (ISCAS)
Presentations:
  • “Efficient, Robust, and Heterogeneous Compute-in-Memory for Edge Intelligence”, Texas A&M University CESG seminar, Jan. 2024.
  • “Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator”, IEEE Biomedical Circuits and Systems Conference (BIOCAS), Toronto, ON, Canada, Oct. 2023.
  • “Efficient & Reliable RRAM-based Compute-in-Memory for Edge Intelligence”, In-Memory Architectures and Computing Applications Workshop (iMACAW) at DAC, San Francisco, CA, Jul. 2023.
  • “Efficient and Reliable Vision Accelerator with Compute-in-Memory”, ACM/IEEE DAC Ph.D. Forum, San Francisco, CA, Jul. 2023
  • “Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array”, IEEE Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, Jun. 2023.
  • “Efficient and Reliable Edge Vision Accelerator with Compute-in-Memory”, Georgia Tech Chips Day, Atlanta, GA, May 2023.
  • “RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers”, ACM/IEEE Design, Automation & Test in Europe (DATE), Antwerp, Belgium, Apr. 2023.
  • “Efficient and Reliable Edge Vision Accelerator with Compute-in-Memory”, ACM/IEEE DATE Ph.D. Forum, Antwerp, Belgium, Apr. 2023.
  • “A 40nm RRAM Compute-in-Memory Macro with On-Chip Write-Verify, Temperature-Independent ADC References, and In-Situ Error Correction”, SRC TECHCON, Austin, TX, Sep. 2022.
  • “RRAM-based Compute-in-Memory Macro with Temperature-Independent ADC References and Parallelism-Preserving MAC-ECC”, SRC ASCENT Center annual review, Notre Dame, IN, Aug. 2022.
  • “Temporal Frame Filtering with Near-Pixel Compute for Autonomous Driving”, IEEE Conference on Artificial Intelligence Circuits and Systems (AICAS), virtual, Jun. 2022.
  • “In-Situ Error Correction for Reliable NVM-Based CIM Inference Engines”, SRC ASCENT Center seminar, virtual, Jan. 2022.
  • “A 40nm MLC-RRAM CIM Macro with Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References”, IBM AI Hardware Forum, virtual, Oct. 2021.
  • “A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References”, IEEE European Solid State Circuits Conference (ESSCIRC), virtual, Sep. 2021.
  • “RRAM-based Compute-in-Memory Macro Tape-out”, SRC ASCENT Center annual review, virtual, Aug. 2021.
  • “Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security”, IEEE Custom Integrated Circuits Conference (CICC), virtual, Apr. 2021.
  • “RRAM-CIM Design with Reconfigurability and Embedded Security”, TSMC, virtual, Jun. 2020.