Wantong Li

Dr. Wantong Li

Biosketch

Wantong Li is an assistant professor of electrical and computer engineering at the University of California, Riverside, where he directs the Intelligent Computing Architecture and Nanosystem (ICAN) Group. He received the B.S. degree in electrical engineering from Washington University in St. Louis in 2015, and the M.S. degree in electrical engineering from Columbia University in 2016. He obtained the Ph.D. degree from Georgia Institute of Technology, where he was advised by Prof. Shimeng Yu. From 2017 to 2019, he worked as an IC design engineer at Power Integrations and Micron Technology. He also held internship positions at AMD, MediaTek, Roche Diagnostics, and bioMérieux.

Education

  • Ph.D., electrical and computer engineering, Georgia Institute of Technology, 2024
  • M.S., electrical engineering, Columbia University, 2016
  • B.S., electrical engineering, Washington University in St. Louis, 2015

Honors and Awards

  • Regents Faculty Fellowship, UCR Academic Senate
  • DAC 2025 Outstanding TPC Member Award
  • ECE Interdisciplinary Research (INSPIRE) Fellowship, Georgia Tech
  • School of ECE Fellowship, Georgia Tech
  • Nikola Tesla Scholarship, Columbia University
  • Sigma Xi (Scientific Research Society)
  • Eta Kappa Nu (Electrical and Computer Engineering Honor Society)
  • Tau Beta Pi (Engineering Honor Society)

Service

Conference & Workshop Organizing Committee :
  • In-Memory Architectures and Computing Applications Workshop (iMACAW) at DAC, Organizing Committee, 2025
  • ACM/IEEE, Design Automation Conference (DAC), Session Co-Chair, 2025
  • ACM, Great Lakes Symposium on VLSI (GLSVLSI), Session Chair, 2025
  • IEEE International Symposium on Workload Characterization (IISWC), Poster Chair, 2025
Conference Technical Program Committee & Reviewer:
  • ACM/IEEE, Design Automation Conference (DAC), Technical Program Committee, 2025, 2026
  • ACM/IEEE, International Conference on Computer-Aided Design (ICCAD), Technical Program Committee, 2025
  • ACM/IEEE, Design, Automation and Test in Europe Conference (DATE), Technical Program Committee, 2026
  • IEEE, International Midwest Symposium on Circuits and Systems (MWSCAS), Track Chair, 2025
  • IEEE, Computer Society Annual Symposium (ISVLSI), Technical Program Committee, 2025
  • ACM, International Symposium on Computer Architecture (ISCA), Reviewer, 2026
  • IEEE, IEEE International Symposium on High-Performance Computer Architecture (HPCA), Artifact Reviewer, 2026
  • ACM, Great Lakes Symposium on VLSI (GLSVLSI), Technical Program Committee, 2025
  • IEEE, International Conference on VLSI Design (VLSID), Technical Program Committee, 2025, 2026
  • IEEE, International Conference on Artificial Intelligence Circuits and Systems (AICAS), Reviewer, 2023, 2024, 2025
  • IEEE, Biomedical Circuits and Systems Conference (BioCAS), Reviewer, 2025
  • IEEE, International Symposium on Circuits and Systems (ISCAS), Reviewer, 2024, 2025, 2026
Paper Reviews:
  • IEEE, Computer Architecture Letters (CAL)
  • IEEE, Electron Device Letters (EDL)
  • IEEE, Journal of Solid-State Circuits (JSSC)
  • IEEE, Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)
  • IEEE, Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC)
  • IEEE, Transactions on Biomedical Circuits and Systems (TBioCAS)
  • IEEE, Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
  • IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)
  • IEEE, Transactions on Circuits and Systems for Artificial Intelligence (TCASAI)
  • IEEE, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
  • IEEE, Transactions on Computers (TC)
  • IEEE, Transactions on Very Large Scale Integration (TVLSI)
  • MDPI, Electronics
  • MDPI, Micromachines
  • MDPI, Sensors
  • Springer, The Journal of Supercomputing
Presentations:
  • “Driving AI Efficiency through Heterogeneously Integrated Memory-Centric Computing”, ECE Seminar, UC Riverside, Nov 2025.
  • “Driving AI Efficiency through Heterogeneously Integrated Data-Centric Computing”, Mondays in Memory (MiM) webinar, Jul 2025.
  • “RandEye: On-Sensor Stochastic Image Transformation for Backdoor-Resistant Edge Inference”, ACM Great Lakes Symposium on VLSI (GLSVLSI), New Orleans, LA, Jun 2025.
  • “Driving AI Efficiency through Heterogeneously Integrated Memory-Centric Computing”, ECE Seminar, UC Riverside, Feb 2025.
  • “Driving AI Efficiency through Heterogeneously Integrated Memory-Centric Computing”, CSE Colloquium, UC Riverside, Dec 2024.
  • “Driving AI Efficiency through Memory-Centric Computing”, Computer Architecture Seminar, University of Hawaiʻi at Mānoa, Nov 2024.
  • “Computer Engineering from Semiconductor’s Perspective”, CEN Student Orientation, UC Riverside, Sep 2024.
  • “Efficient, Robust, and Heterogeneous Compute-in-Memory for Edge Intelligence”, Texas A&M University CESG seminar, Jan 2024.
  • “Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator”, IEEE Biomedical Circuits and Systems Conference (BIOCAS), Toronto, ON, Canada, Oct 2023.
  • “Efficient & Reliable RRAM-based Compute-in-Memory for Edge Intelligence”, In-Memory Architectures and Computing Applications Workshop (iMACAW) at DAC, San Francisco, CA, Jul 2023.
  • “Efficient and Reliable Vision Accelerator with Compute-in-Memory”, ACM/IEEE DAC Ph.D. Forum, San Francisco, CA, Jul 2023
  • “Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array”, IEEE Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, Jun 2023.
  • “Efficient and Reliable Edge Vision Accelerator with Compute-in-Memory”, Georgia Tech Chips Day, Atlanta, GA, May 2023.
  • “RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers”, ACM/IEEE Design, Automation & Test in Europe (DATE), Antwerp, Belgium, Apr 2023.
  • “Efficient and Reliable Edge Vision Accelerator with Compute-in-Memory”, ACM/IEEE DATE Ph.D. Forum, Antwerp, Belgium, Apr 2023.
  • “A 40nm RRAM Compute-in-Memory Macro with On-Chip Write-Verify, Temperature-Independent ADC References, and In-Situ Error Correction”, SRC TECHCON, Austin, TX, Sep 2022.
  • “RRAM-based Compute-in-Memory Macro with Temperature-Independent ADC References and Parallelism-Preserving MAC-ECC”, SRC ASCENT Center annual review, Notre Dame, IN, Aug 2022.
  • “Temporal Frame Filtering with Near-Pixel Compute for Autonomous Driving”, IEEE Conference on Artificial Intelligence Circuits and Systems (AICAS), virtual, Jun 2022.
  • “In-Situ Error Correction for Reliable NVM-Based CIM Inference Engines”, SRC ASCENT Center seminar, virtual, Jan 2022.
  • “A 40nm MLC-RRAM CIM Macro with Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References”, IBM AI Hardware Forum, virtual, Oct 2021.
  • “A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References”, IEEE European Solid State Circuits Conference (ESSCIRC), virtual, Sep 2021.
  • “RRAM-based Compute-in-Memory Macro Tape-out”, SRC ASCENT Center annual review, virtual, Aug 2021.
  • “Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security”, IEEE Custom Integrated Circuits Conference (CICC), virtual, Apr 2021.
  • “RRAM-CIM Design with Reconfigurability and Embedded Security”, TSMC, virtual, Jun 2020.
Proposal Review:
  • NSF Panel Review, 2025, 2026
  • UCR Minigrant Review, 2026
University Service:
  • Tau Beta Pi UCR Chapter, Chief Advisor, 2025 – Present
  • UCR ECE Graduate Advisor, 2025 – Present