Announcement13
Our paper “A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays” is recognized as a highlight paper at Symposium of VLSI.
Our paper “A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays” is recognized as a highlight paper at Symposium of VLSI.